C35B4C3
Main Features
- Mature CMOS technology
- Fully compatible with the 0.35µm base process licensed from TSMC
- Gate density of 23k/mm²
- Well-suitable for digital, analog and mixed-signal systems
Technology Characteristics
- 0.35µm technology node
- 200mm wafer size
- 20 masks
- P-type substrate
- LOCOS isolation
- 3.3V and 5V operating voltages
- 4 metal (Al) layers for interconnexion
- Second poly layer for resistors and capacitors
- High-resistive poly (1.2kohms/square)
- Poly-insulator-poly capacitor (0.9fF/µm²)
- 1 GHz max operating frequency
- Qualified from -40°C to 125°C, for automotive and medical markets
RAM, EEPROM and OTP memories (poly fuses) available on request
Wafer cross section
Prices
- 640 euros/mm²
- 580 euros/mm² for registered Europractice member
- Minimum billing area of 7 mm²
- Delivery of 40 bare dies
Contact
Design-Kit Content
Basic libraries :
- Primitive devices
- Primitive RF devices
- Primitive ESD devices
Analog libraries :
- Low-voltage analog standard cells
- 4 metal analog power supply pads & analog I/O pads
- 4 metal 3-bus analog power supply pads & analog I/O pads
- Core-limited 4 metal 3-bus analog power supply pads & analog I/O pads
Digital libraries :
- 3.3V digital standard core cells
- Dense 3.3V digital standard core cells
- 5V digital standard core cells
- 3-bus 3.3V digital standard cells
- Dense 3-bus 3.3V digital standard cells
- 3-bus 5V digital standard core cells
- 4 metal digital input/output/bidirectional buffers & power pads – 3.3V supply
- 4 metal digital input/output/bidirectional buffers & power pads – 5V supply
- 4 Metal 3-Bus digital input/output/bidirectional buffers & power pads – 3.3V supply
- Core-limited 4 metal 3-bus digital input/output/bidirectional buffers & power pads – 3.3V supply
- Core-limited 4 metal digital input/output/bidirectional buffers & power pads – 5V supply
CAD Tools
Cadence
- Virtuoso ADE suite (design exploration and analysis)
- Genus (physical synthesis)
- Spectre (electrical simulation)
- Xcelium (logic simulation)
- Assura (physical verification)
- Quantus (parasitic extraction)
- Voltus (power analysis)
- Innovus (digital implementation)
Siemens
- Calibre (physical verification)
- QuestaSim (logic simulation)
- QuestaFormal (formal verification)
Synopsys
- VTRAN (design exploration and analysis)
- Design compiler (physical synthesis)
- PrimeTime (static timing analysis)
- HSpice (electrical simulation)
Run Dates
- 3 MPW runs per year: usually in February, July and November.
- Next submission deadline to CIME-P: please refer to the run schedule.
Turnaround Time
- 12 weeks from foundry tape-out to wafer fab-out
- 5 additional weeks for wafer dicing and chip packaging