atC18D6S7
Main Features
- Mature CMOS technology
- Based on TSMC low-voltage CMOS technology
- Gate density of 150k/mm²
- Optimized for complex mixed-signal designs
Technology Characteristics
- 0.18µm technology node
- 200mm wafer size – Premstätten fab (Austria)
- 29 masks
- P-type substrate
- Shallow Trench Isolation (STI)
- Triple well
- 40A and 138A gate oxides
- 1 poly layer
- 6 metal (Al) layers for interconnexion
Device Characteristics
- 1.8V and 5.0V operating voltages
- 4 GHz max operating frequency
- Qualified from -40°C to 125°C
- MOS transistors optimized for mixed-signal applications
- Vertical npn & pnp bipolar transistors
- High-resistive poly (3kΩ/square)
- Metal-insulator-metal capacitor (2fF/µm²)
RAM, EEPROM and OTP memories (poly fuses) available on request
Design-Kit Content
- TECH_TC18D6 : technology and site type definitions
- PRIMLIB : primitive devices
- CORELIBT : standard digital core cells, substrate based
- CORELIB_DNW : digital core cells deep nwell, floating
- CORELIBT_5V : digital core cells, 5.0V
- IOLIBC_6M : digital peripheral cells
- IOLIBC_3B_6M : digital peripheral cells, 3-bus
- ESDLIB : ESD devices
Prices
- 1,650 euros/mm²
- 1,500 euros/mm² for registered Europractice member
- Minimum billing area of 5.5 mm²
- Delivery of 40 bare dies
Contact
CAD Tools
Cadence
- Virtuoso ADE suite (design exploration and analysis)
- Genus (physical synthesis)
- Spectre/Ultrasim (electrical simulation)
- Xcelium (logic simulation)
- Assura (physical verification)
- QRC (parasitic extraction)
- Voltus (power analysis)
- Innovus (digital implementation)
Siemens
- Calibre (physical verification)
- QuestaSim (logic simulation)
- QuestaFormal (formal verification)
Synopsys
- Design compiler (physical synthesis)
- PrimeTime (static timing analysis)
- Tetramax (ATE testing)
Usual Application areas
Smart sensors, sensor interface devices, smart metering devices, industrial and building controls, and LED lighting control, etc.
Run Dates
- 2 MPW runs per year
- Usually in April and October
- Next submission deadline to CIME-P: please refer to the run schedule.
Turnaround Time
- 18 weeks from foundry tape-out to wafer fab-out
- 5 additional weeks for wafer dicing and chip packaging